1. Field of the Invention
The present invention relates to an electrode substrate including a transparent conductive layer which is in contact with both an inorganic insulating region formed of an inorganic insulating layer and an organic insulating region formed of an organic insulating layer, a method for producing the same, and a display device including the same.
2. Description of the Related Art
A transparent conductive layer including ITO (indium tin oxide) is usable as an electrode for allowing light to transmit therethrough and controlling light transmission. Attempts have been made to practically use an electrode substrate having such a transparent conductive layer in, for example, display devices including electroluminescence display devices, touch panels, and solar cells.
An exemplary display device including an electrode substrate having a transparent conductive layer both on an organic insulating layer and an inorganic insulating layer is a liquid crystal display device. A liquid crystal display device is now actively studied as a type of flat panel display for replacing a CRT display. The liquid crystal display device has already been practically used in a battery-driven super-compact TV, a notebook computer or the like. Hereinafter, a liquid crystal display device including an electrode substrate including a transparent conductive layer provided on both an organic insulating layer and an inorganic insulating layer will be described.
FIG. 1 schematically shows a basic structure of a liquid crystal display device 100. The liquid crystal display device 100 is of an active matrix TFT array type, using thin film transistors (TFT) as switching devices. Such a type of display device is advantageous to provide a high quality display.
As shown in FIG. 1, the liquid crystal display device 100 includes an upper substrate 102, a lower substrate 101 as an electrode substrate, and a liquid crystal layer 109 interposed between the upper substrate 102 and the lower substrate 101. Liquid crystal molecules in the liquid crystal layer 109 are controlled by the upper substrate 102 and the lower substrate 101.
The lower substrate 101 includes an insulating plate 20; and a plurality of gate lines 105, a plurality of source lines 106, a plurality of pixel electrodes 103, and a plurality of TFTs 108 respectively provided in correspondence with the plurality of pixel electrodes 103, which are provided on the insulating plate 20. The plurality of pixel electrodes 103 are each connected to the corresponding gate line 105 and the corresponding source line 106 through the corresponding TFT 108.
FIG. 2 is a plan view of the lower substrate 101. The planar region of the lower substrate 101 includes a display region 150 (hatched in FIG. 2) and a peripheral region 160. The display region 150 includes the plurality of pixel electrodes 103 and the plurality of TFTs 108 for controlling the pixel electrodes 103 connected thereto. The pixel electrodes 103 are each formed of a transparent conductive layer. Since the liquid crystal display device 100 (FIG. 1) is of a transmission type, at least a part of the insulating plate 20 is formed of a transparent material, and the pixel electrodes 103 are formed of a transparent conductive material, so that an image is displayed using light (generally, light from a light source) passing to the display side from the side opposite to the display side of the liquid crystal display device 100. In this manner, the light is transmitted and controlled. The liquid crystal display device 100 (FIG. 1) is of a transparent type, but the description here is applicable to a transmission region of a liquid crystal display device of a transmission/reflection type.
The peripheral region 160 includes a plurality of gate connection terminals 110, a plurality of source connection terminals 120, and a plurality of common connection terminals 130. The plurality of gate connection terminals 110 are respectively connected to the plurality of gate lines 105; the plurality of source connection terminals 120 are respectively connected to the plurality of source lines 106; and the plurality of common connection terminals 130 are respectively connected to a plurality of common lines 107. The gate lines 105, the source lines 106 and the common lines 107 are provided in the peripheral region 160 and extend to the display region 150. In this specification, each gate connection terminal 110 and the vicinity thereof will be referred to as a xe2x80x9cgate connection terminal area 111xe2x80x9d, each source connection terminal 120 and the vicinity thereof will be referred to as a xe2x80x9csource connection terminal area 121xe2x80x9d, and each common connection terminal 130 and the vicinity thereof will be referred to as a xe2x80x9ccommon connection terminal area 131xe2x80x9d. The gate connection terminal areas 111, source connection terminal areas 121 and the common connection terminal area 131 will be collectively referred to as a xe2x80x9cperipheral terminal areaxe2x80x9d.
FIG. 3 is an enlarged plan view of the display region 150 of the lower substrate 101. One pixel electrode 103 is indicated by a dashed line in FIG. 3. The gate lines 105 and the common lines 107 are provided parallel to each other, and the source lines 106 are provided perpendicular to the gate lines 105 and the common lines 107. In the vicinity of an intersection of each gate line 105 and each source line 106, the gate line 105 is branched to be connected to a gate electrode of the TFT 108, and the source line 106 is branched to be connected to a source electrode of the TFT 108. A connection electrode 48 which is connected to a drain electrode of the TFT 108 is provided to partially overlap the corresponding common line 107. An area in which the connection electrode 48 and the common line 107 overlap each other has a contact hole 50.
FIG. 4 is a cross-sectional view of the display region 150 of the substrate 101 along line A-Axe2x80x2 in FIG. 3. In FIG. 4, the area including the gate line 105 and the vicinity thereof will be referred to as a xe2x80x9cTFT areaxe2x80x9d, and the area including the common electrode 107 and the vicinity thereof will be referred to as a xe2x80x9ccontact hole areaxe2x80x9d.
In the TFT area, the gate line 105 (more specifically, the branched portion of the gate line 105) is provided on the insulating plate 20. A gate insulating layer 44 is provided on the insulating plate 20 so as to cover the gate line 105. The gate insulating layer 44 can be formed of silicon nitride (SiNx). An amorphous semiconductor layer 45 is provided on the gate insulating layer 44, and the source electrode 46a and the drain electrode 46b of the TFT 108 are provided on the amorphous semiconductor layer 45 with a gap interposed therebetween. As described above, the source electrode 46a is connected to the source line 106, and the drain electrode 46b is connected to the connection electrode 48. The TFT 108 including the above-described elements is covered with an organic insulating layer 49 formed of a transparent material. The organic insulating layer 49 has a flat top face, and the pixel electrode 103 is provided on the organic insulating layer 49.
In the contact area, the common electrode 107 is provided on the insulating plate 20, and the gate insulating layer 44 is provided on the insulating plate 20 so as to cover the common electrode 107. The gate insulating layer 44 is covered with the connection electrode 48. The gate insulating layer 44 is covered with the organic insulating layer 49. The pixel electrode 103 is provided on the organic insulating layer 49. The contact hole 50 is provided so that the connection electrode 48 and the pixel electrode 103 are in direct contact with each other.
The above-described structure of the display region 150 provides a high numerical aperture mainly for the following two reasons. (1) Since the surface of the organic insulating layer 49 on which the pixel electrode 103 is provided is flat, the display defect (domain phenomenon) caused by an alignment disturbance of liquid crystal molecules in the liquid crystal layer 109 (FIG. 1) at a step portion at an each end of the pixel electrode over the TFT 108 is alleviated, and thus the effective display area in the liquid crystal layer can be increased. (2) Since the organic insulating layer 49 underlying the pixel electrode 103 is relatively thick with a thickness of 0.3 xcexcm to 2 xcexcm, the pixel electrode 103 on the organic insulating layer 49 (on the display side) and the gate line 105/the source line 106 on the other side of the organic insulating layer 49 from the pixel electrode 103 do not shortcircuit each other. Therefore, the pixel electrodes 103 can be provided so as to overlap the gate line 105, the source line 106 and other lines when seen from the display side, and thus the area of the pixel electrode 103 can be increased.
In general, in the peripheral region 160 (FIG. 2), a transparent conductive layer is provided on an inorganic insulating layer which is a part of the electrode. The transparent conductive layer provided on the inorganic insulating layer prohibits oxidation of the peripheral terminal area and the resulting increase in the resistance of the gate connection terminals 110, the source connection terminals 120 and the common connection terminals 130. It is possible to provide these terminals 110, 120 and 130 in the peripheral terminal area on the organic insulating layer, but it is not preferable since defective connection with other components may occur to reduce the reliability and the organic insulating layer can undesirably become brittle.
The transparent conductive layer is generally wet-etched. Dry-etching is not preferable for the following reasons. (1) Dry-etching will change the quality of the organic insulating layer and thus the insulating quality is deteriorated. (2) In the case where the electrode substrate described above is used for a liquid crystal display device, a liquid crystal layer can undesirable be contaminated by the dry-etching residue, deteriorating the display quality. In this specification, the term xe2x80x9cetchingxe2x80x9d refers to xe2x80x9cwet-etchingxe2x80x9d unless otherwise specified.
In this specification, the term xe2x80x9cetching shiftxe2x80x9d refers to a length of a layer which is removed by etching. An etching shift per unit time is referred to as an xe2x80x9cetching ratexe2x80x9d.
It might be considered that the transparent conductive layer provided on the organic insulating layer and the transparent conductive layer provided on the inorganic insulating layer can be etched simultaneously, i.e., in the same step. In practice, however, it is not preferable for the following reason. Etching shifts of the two transparent conductive layers are different. When the transparent conductive layer on the organic insulating layer and the transparent conductive layer provided on the inorganic insulating layer are designed to be a substantially identical size and etched in a similar manner, the two transparent conductive layers become different in size due to the different etching shifts, i.e., the different rates. As a result, as shown in FIG. 5, the designing size and the finally resulting size of one of the transparent conductive layers become different. Accordingly, the two transparent conductive layers cannot be etched in the same step.
With reference to FIG. 6, a method for producing the pixel electrode 103 (transparent conductive layer), the gate connection terminal 110, the source connection terminal 120 and the common connection terminal 130 of the electrode substrate 101 shown in FIG. 2 will be described. Regarding the pixel electrode 103, specifically a portion thereof in the TFT 108 area is shown in FIG. 6. The other portion of the pixel electrode 103 is produced in substantially the same manner.
In step (a), a transparent conductive layer 155 (formed, for example, ITO) is formed in the TFT area and the peripheral region 160 in the same step.
The transparent conductive layer 155 in the TFT area, which is to become the pixel electrode 103, is formed on the flat surface of the organic insulating layer 49.
In each of the gate and common connection terminal areas 111 and 131 of the peripheral region 160, the gate line 105 or the common line 107 is formed on the insulating plate 20. An inorganic insulating layer 144 is formed on the gate line 105 or the common line 107, although the inorganic insulating layer 144 is not provided on the center of the gate line 105 or the common line 107. On the center of the gate line 105 or the common line 107, an electrode 154 is formed. Then, a transparent conductive layer 155 is formed on the inorganic insulating layer 144 so as to cover the electrode 154. The transparent conductive layer 155 is to become a transparent conductive layer 157 having a stable connection resistance.
In step (b), photoresist patterning is performed in the peripheral region 160 as follows. First, a first photoresist layer 165 is formed on an area of the transparent conductive layer 155, which is to be left (i.e., the area to become a transparent conductive layer 157). The first photoresist layer 165 is formed of a positive resist, for example, of a novolac resin available from Tokyo Ohka Kogyo Co., Ltd. In step (b), in the TFT area, the first photoresist layer 165 is formed on the entire surface of the transparent conductive layer 155.
In step (c), in the peripheral region 160, the transparent conductive layer 155 is removed by wet-etching except for the area covered with the first photoresist layer 165.
In step (d), the first photoresist layer 165 is removed. The transparent electrode 157 formed of the transparent conductive layer 155 is formed in the peripheral region 160, whereas the transparent conductive layer 155 remains without being removed even partially in the TFT area.
In step (e), photoresist patterning is performed in the TFT area. First, a second photoresist layer 167 is formed on an area of the transparent conductive layer 155, which is to be left (i.e., the area which is to become the pixel electrode 103). The second photoresist layer 167 is formed of a positive resist, for example, of a novolac resin available from Tokyo Ohka Kogyo Co., Ltd. In step (e), in the peripheral region 160, the second photoresist layer 167 is formed on the entire surface of the resultant laminate.
In step (f), in the TFT area, the transparent conductive layer 155 is removed by wet-etching except for the area covered with the second photoresist layer 167.
In step (g), the second photoresist layer 167 is removed, thereby forming the pixel electrode 103.
As described above, the transparent conductive layer 155 on the inorganic insulating layer 144 and the transparent conductive layer 155 on the organic insulating layer 49 need to be etched separately (steps (c) and (f)) due to the different etching rates.
In order to solve the above-described inconvenience, for example, use of plasma treatment, has been proposed as follows.
Japanese Laid-Open Publication No. 9-152625 discloses a method for producing an electrode substrate by treating an organic insulating layer with an oxygen plasma and then forming a transparent conductive layer in order to improve the adherence between the organic insulating layer and the transparent conductive layer.
Japanese Laid-Open Publication No. 11-283934 discloses a method of treating an organic insulating layer with a gas such as, for example, CF4+O2 in order to improve the electric connection between the pixel electrode and the drain electrode which are connected through a contact hole formed in the organic insulating layer, so as to enhance the display quality. However, use of the mixture gas of CF4+O2 or the like for plasma treatment raises the etching rate of the transparent conductive layer on the organic insulating layer. Therefore, again, the transparent conductive layer on the organic insulating layer and the transparent conductive layer on the inorganic insulating layer cannot be etched in the same step.
According to one aspect of the invention, a method for producing an electrode substrate, having an organic insulating region formed of an organic insulating material and an inorganic insulating region formed of an inorganic insulating material on an identical side thereof, includes the steps of performing a plasma treatment of the organic insulating region; forming a first transparent conductive layer in contact with the organic insulating region and a second transparent conductive layer in contact with the inorganic insulating region; and etching the first transparent conductive layer and the second transparent conductive layer in the same step.
In one embodiment of the invention, the step of performing the plasma treatment includes the step of performing a plasma treatment of the inorganic insulating region in the same step with the plasma treatment of the organic insulating region.
In one embodiment of the invention, the plasma treatment is selected from the group consisting of an oxygen plasma treatment, an Ar plasma treatment and a CF4 plasma treatment.
In one embodiment of the invention, the plasma treatment includes the step of performing an oxygen plasma treatment and the step of performing an Ar plasma treatment following the step of performing the oxygen plasma treatment.
In one embodiment of the invention, the plasma treatment includes the step of performing an oxygen plasma treatment and the step of performing a CF4 plasma treatment following the step of performing the oxygen plasma treatment.
In one embodiment of the invention, the plasma treatment makes a root-mean-square of a surface roughness of the organic insulating layer 1.0 nm or less.
In one embodiment of the invention, the method for producing an electrode substrate further includes the step of heat-treating the first transparent conductive layer and the second transparent conductive layer after the step of plasma treatment.
In one embodiment of the invention, the heat-treatment is performed at a temperature of 150xc2x0 C. or higher and 220xc2x0 C. or lower.
According to another aspect of the invention, a method for producing an electrode substrate, having an organic insulating region formed of an organic insulating material and an inorganic insulating region formed of an inorganic insulating material on an identical side thereof, includes the steps of forming a first transparent conductive layer in contact with the organic insulating region and a second transparent conductive layer in contact with the inorganic insulating region so that the first transparent conductive layer has a crystal grain size of 20 nm or more and 50 nm or less; and etching the first transparent conductive layer and the second transparent conductive layer in the same step.
In one embodiment of the invention, the first transparent conductive layer has a crystal grain size of 20 nm or more and 40 nm or less.
In one embodiment of the invention, the method for producing an electrode substrate further includes the step of performing a plasma treatment of the organic insulating region before the first transparent conductive layer is formed.
According to still another aspect of the invention, a method for producing an electrode substrate, having an organic insulating region formed of an organic insulating material and an inorganic insulating region formed of an inorganic insulating material on an identical side thereof, includes the steps of forming a first transparent conductive layer in contact with the organic insulating region and a second transparent conductive layer in contact with the inorganic insulating region; heat-treating the first transparent conductive layer and the second transparent conductive layer; and etching the first transparent conductive layer and the second transparent conductive layer in the same step.
In one embodiment of the invention, the heat-treatment is performed at a temperature of 150xc2x0 C. or higher and 220xc2x0 C. or lower which is maintained for a certain period of time.
In one embodiment of the invention, the heat-treatment is performed at a temperature of 200xc2x0 C. or higher and 220xc2x0 C. or lower which is maintained for a certain period of time.
According to still another aspect of the invention, a electrode substrate includes an organic insulating region formed of an organic insulating material and having a root-mean-square of a surface roughness of 1.0 nm or less; an inorganic insulating region formed of an inorganic insulating material provided on an identical side with the organic insulating region; and a first transparent conductive layer in contact with the organic insulating region and a second transparent conductive layer in contact with the inorganic insulating region.
In one embodiment of the invention, the root-mean-square of the surface roughness of the organic insulating region is 0.28 nm or more and 1.0 nm or less.
In one embodiment of the invention, the first transparent conductive layer has a crystal grain size of 20 nm or more and 50 nm or less.
In one embodiment of the invention, the first transparent conductive layer has a crystal grain size of 20 nm or more and 40 nm or less.
According to still another aspect of the invention, a display device includes any of the above-described electrode substrates.
According to still another aspect of the invention, an electrode substrate includes an organic insulating region formed of an organic insulating material; an inorganic insulating region formed of an inorganic insulating material provided on an identical side with the organic insulating region; and a first transparent conductive layer in contact with the organic insulating region and a second transparent conductive layer in contact with the inorganic insulating region. The first transparent conductive layer has a crystal grain size which is set so that the first transparent conductive layer and the second transparent conductive layer have substantially an equal shift rate.
In one embodiment of the invention, the first transparent conductive layer has a crystal grain size of 20 nm or more and 50 nm or less.
In one embodiment of the invention, the first transparent conductive layer has a crystal grain size of 20 nm or more and 40 nm or less.
According to still another aspect of the invention, a display device includes any of the above-described electrode substrates.
Thus, the invention described herein makes possible the advantages of providing a method for producing an electrode substrate by which a transparent conductive layer in contact with on an organic insulating layer formed of an organic insulating material and a transparent conductive layer in contact with an inorganic insulating layer formed of an inorganic insulating material can be etched in substantially simultaneously, an electrode substrate produced by such a method, and a display device including such an electrode substrate. The above-described method is realized by performing (1) plasma treatment performed before the transparent conductive layer is formed, (2) control of the crystal grain size of the transparent conductive layer, (3) heat-treatment (i.e., annealing) of the transparent conductive layer, and (4) a combination of at least two of (1) through (3).
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.